/* 
 -- ============================================================================
 -- FILE NAME	: chip_top_test.v
 -- DESCRIPTION : 
 -- ----------------------------------------------------------------------------
 -- Revision  Date		  Coding_by	 
 -- 1.0.0	  2012/04/02  suito		 
 -- ============================================================================
*/

  
`timescale 1ns/1ps	

`include "nettype.h"
`include "stddef.h"
`include "global_config.h"  
`include "bus.h"
`include "cpu.h"
`include "gpio.h"
  
module chip_top_test;  
	reg						clk_ref;	  
	reg						reset_sw;	   
`ifdef IMPLEMENT_UART
	wire					uart_rx;	   
	wire					uart_tx;	   
`endif
`ifdef IMPLEMENT_GPIO
`ifdef GPIO_IN_CH
	wire [`GPIO_IN_CH-1:0]	gpio_in = {`GPIO_IN_CH{1'b0}};
`endif
`ifdef GPIO_OUT_CH
	wire [`GPIO_OUT_CH-1:0] gpio_out;					  
`endif
`ifdef GPIO_IO_CH
	wire [`GPIO_IO_CH-1:0]	gpio_io = {`GPIO_IO_CH{1'bz}};
`endif
`endif
						   
`ifdef IMPLEMENT_UART
	wire					 rx_busy;		
	wire					 rx_end;		  
	wire [`ByteDataBus]		 rx_data;		 
`endif

	  
	parameter				 STEP = 100.0000;
  
	always #( STEP / 2 ) begin
		clk_ref <= ~clk_ref;
	end

	    
	chip_top chip_top (
		.clk_ref	(clk_ref),
		.reset_sw	(reset_sw)
		/********** UART **********/
`ifdef IMPLEMENT_UART //
		, .uart_rx	(uart_rx)
		, .uart_tx	(uart_tx)
`endif  
`ifdef IMPLEMENT_GPIO //
`ifdef GPIO_IN_CH			   // 
		, .gpio_in	(gpio_in)  // 
`endif
`ifdef GPIO_OUT_CH	 // 
		, .gpio_out (gpio_out) // 
`endif
`ifdef GPIO_IO_CH	 // 
		, .gpio_io	(gpio_io)  // 
`endif
`endif
);

	  	
`ifdef IMPLEMENT_GPIO
`ifdef GPIO_IN_CH
	always @(gpio_in) begin	
		$display($time, " gpio_in changed  : %b", gpio_in);
	end
`endif
`ifdef GPIO_OUT_CH
	always @(gpio_out) begin
		$display($time, " gpio_out changed : %b", gpio_out);
	end
`endif
`ifdef GPIO_IO_CH
	always @(gpio_io) begin
		$display($time, " gpio_io changed  : %b", gpio_io);
	end
`endif
`endif
  	
`ifdef IMPLEMENT_UART // 
	    
	assign uart_rx = `HIGH;	
//	  assign uart_rx = uart_tx;
  	
	uart_rx uart_model (  
		.clk	  (chip_top.clk),		 // 
		.reset	  (chip_top.chip_reset), // 
		.rx_busy  (rx_busy),			 // 
		.rx_end	  (rx_end),				 // 
		.rx_data  (rx_data),			 // 
		/********** Receive Signal **********/
		.rx		  (uart_tx)				 // 
	);

	always @(posedge chip_top.clk) begin
		if (rx_end == `ENABLE) begin // 
			$write("%c", rx_data);
		end
	end
`endif

	    
	initial begin
		# 0 begin
			clk_ref	 <= `HIGH;
			reset_sw <= `RESET_ENABLE;
		end
		# ( STEP / 2 )
		# ( STEP / 4 ) begin		 
			$readmemh(`ROM_PRG, chip_top.chip.rom.x_s3e_sprom.mem);
			$readmemh(`SPM_PRG, chip_top.chip.cpu.spm.x_s3e_dpram.mem);
		end
		# ( STEP * 20 ) begin		 
			reset_sw <= `RESET_DISABLE;
		end
		# ( STEP * `SIM_CYCLE ) begin
			$finish;
		end
	end
  	
	initial begin
		$dumpfile("chip_top.vcd");
		$dumpvars(0, chip_top);
	end
  
endmodule	
